A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes

SRAM has become one of the most critical blocks in current System on Chip (SoC) designs. Due to the rise of AI and ML applications, the importance of SRAM has grown, as it handles fast, repeated data write and read operations. AI and ML applications need a huge amount of data to be stored and retrieved from memory. Hence, the speed and efficiency of the on-chip SRAMs define the overall performance. In today’s SoCs, memory arrays occupy close to 50-70% of the total die area. Hence, optimizing each bitcell area becomes crucial to save the die area and cost. Different applications need different topologies of SRAM bitcells. The 6T bitcell is most widely used because it offers a balance of speed and density. 8T and 10T SRAM cells are used when leakage and read stability are major concerns. Layout techniques for these bitcells have evolved with technological advancements from planar to FinFET nodes. Foundries develop their own proprietary bitcell layouts, design rules, and device optimization techniques with special layers and masks. Hence, they are treated as proprietary IPs and are not easily accessible for independent researchers and academicians unless they buy the bitcell kit. This highlights the necessity of developing custom bitcells for academic study. Through custom designs, researchers can propose and evaluate new bitcell architectures. This paper aims to compile and present layout design techniques of conventional and widely used 6T single-port, 8T dual-port, 8T two-port, and 10T two-port bitcells in UMC 28 nm Planar CMOS and GPDK 18 nm FinFET nodes.