Via-Optimized CFET 6T SRAM: Performance, Stability, Manufacturability, and Scalability

Tall vias (TVs) in complementary field-effect transistor (CFET) technology pose challenges in performance, defect risk, and scalability due to their high aspect ratio. To address these limitations, we propose a via-optimized CFET 6T static random access memory (SRAM) cell and analyze its electrical characteristics—including delay, energy consumption, and stability—alongside manufacturability and scalability using SPICE simulations. The proposed architecture incorporates a frontside (FS)${V}_{ {ss}}$rail (FS_${V}_{ {ss}}$), a backside bitline (BS_BL), and a partially recessed gate (PRG), enabling reductions in resistance and parasitic capacitance. In particular, the removal of BL TVs (BL TVs) decreases BL (${C}_{\text {bl}}$), wordline (WL) (${C}_{\text {wl}}$), and storage-node ($Q$,${C}_{q}$) capacitances, improving read/write performance and reducing power consumption while maintaining cell stability. Under a slanted via profile down to 88°, the proposed structure tolerates a smaller angle, mitigating metal void risks and demonstrating enhanced manufacturability, whereas the baseline exhibits significant read static noise margin (RSNM) degradation due to increased${V}_{ {ss}}$resistance (${R}_{ {vss}}$). When the contacted poly pitch (CPP) is scaled from 48 to 40 nm, the cell maintains superior read performance with competitive write delay. Overall, the proposed CFET SRAM architecture offers clear advantages in performance, stability, manufacturability, and scalability, providing valuable insights for future CFET 6T SRAM designs.