Monolithically Stackable 1T1C 3-D DRAM: A Technical Survey

This article provides a framework for understanding the state-of-the-art challenges and prospects of monolithically stackable one-transistor–one-capacitor (1T1C) 3-D dynamic random access memory (DRAM). It begins by outlining the limits of 2-D DRAM scaling and the need for monolithic vertical integration, and then examines cell architectures comparing vertical bitline (VBL) and horizontal bitline (HBL) layouts while analyzing charge-loss mechanisms viaoff-state leakage, floating-body-induced parasitic bipolar junction transistor (BJT) activation, and word-line (WL) capacitive coupling. Subsequently, this article reviews access-transistor designs and channel material options from silicon to amorphous semiconductors, along with compatible capacitor geometries and process integration issues. Then, this article extends to array and periphery architectural choices, analyzing WL/BL routing, selector (SL)-assisted sensing, and comparing integration schemes such as CMOS-near-array (CNA), CMOS-under-array (CUA), and CMOS-bonded-array (CBA). The analysis clarifies how routing parasitics, bonding pitch, and thermal budget jointly define the scalability limit of 3-D DRAM. By linking device physics, process integration, and architectural hierarchy into a cohesive framework, this work defines the technological pathways for practical monolithic 3-D DRAM technology for the next decade.