Sub-2 nm Equivalent-Oxide-Thickness Ferroelectric Transistors for Cryogenic Memory and Computing

High Resolution Image Download MS PowerPoint Slide Ferroelectric hafnia-based field-effect transistors are promising candidates for nonvolatile memory and in-memory computing. However, their operation principle under deep-cryogenic conditions at aggressively scaled gate stacks remains underexplored, especially for bulk silicon technology. This work presents an experimental demonstration of front-end-of-line bulk silicon-channel ferroelectric field-effect transistors featuring sub-2 nm equivalent-oxide-thickness gate stacks with ≃5 nm hafnium–zirconium oxide, exhibiting robust switching at 10 K. Key metrics include memory windows exceeding 1 V, tightly distributed threshold voltages (standard deviation ≲ 40 mV), endurance surpassing 10 7 cycles, and retention projections consistent with decade-scale stability. Correlative four-dimensional scanning transmission electron microscopy phase mapping reveals an increased orthorhombic ferroelectric fraction following electrical wake-up at cryogenic temperatures, correlated with enhanced polarization stability and strengthened oxygen–metal coordination. We hypothesize that suppressed trapping-related instability, along with a higher orthorhombic phase, jointly contribute to this effect. Current–voltage sweeps define an operational design window, with memory-window saturation beyond ±5 V programming voltages and ≳900 ns pulse widths, consistent with nucleation-limited reversal kinetics in ultrathin films. A spiking neural network implemented at 10 K achieves >92% classification accuracy on MNIST and 73.8% accuracy on NMNIST data sets, demonstrating practical utility. These findings provide materials- and device-level insights into scaled hafnia FeFETs for energy-efficient cryogenic applications, including potential integration in quantum–classical systems.