Study of n-Channel 4H-SiC MOSFETs with a High-k/SiO2 Stacked Gate Dielectric and a p+-Polysilicon Gate.

In this study, n-channel 4H-SiC MOSFETs with a high-k/SiO2 stacked gate dielectric and a p+-polysilicon gate are proposed and investigated via numerical simulations. The high-k dielectric increases the gate capacitance, thereby reducing the specific on-state resistance of the devices. The p+-polysilicon increases the work-function difference between the gate and the surface p-SiC, which compensates for the threshold voltage reduction caused by the high-k dielectric. Simulation results demonstrate that replacing the SiO2 and n+-polysilicon with an Al2O3/SiO2 stack and p+-polysilicon, respectively, reduces the specific on-resistance by 26.9% while lowering the threshold voltage by only 0.02 V at 25 °C. At 175 °C, the threshold voltage increases by 0.28 V. The temperature coefficient of the threshold voltage is reduced from -6.2 mV/°C to -4.1 mV/°C. In addition, the breakdown voltage, the high-frequency figure of merit, and the switching loss also improve, though the inter-electrode capacitances and the gate-to-drain charge increase. This work provides a practical solution for n-channel 4H-SiC MOSFETs adopting high-k gate dielectrics.