A Survey of FPGA-based 3D CNN Accelerators and Hardware-aware Algorithmic Optimizations

3D Convolutional Neural Networks (3D CNNs) can outperform 2D CNNs on several tasks, including action recognition, video captioning, abnormal event detection, and medical image interpretation. Compared to 2D CNNs, 3D CNNs have a larger number of parameters and higher computational complexity. For this reason, researchers have focused on designing efficient 3D CNN architectures and hardware accelerators. The purpose of this survey is to serve as a guide to recent work on 3D CNNs for action recognition with a focus on FPGA-based accelerators and hardware-aware algorithmic optimizations. We provide an overview of the state-of-the-art in 3D CNN architectures as well as the action recognition datasets used for training and testing the architectures. A performance comparison of 2D versus 3D CNNs on two datasets (Sports-1M and UCF101) is included. We explore the designs of FPGA-based accelerators and compare them in terms of achieved throughput, resource utilization, and power. We survey current methods of optimization for 3D CNN architectures, which are meant to reduce the number of parameters and the memory requirements and to facilitate their deployment on FPGAs. Finally, we highlight current challenges and potential areas of improvement in acceleration of 3D CNNs on FPGA platforms.