Sayantan Dutta, Jyothsnavi Kuppili, Indrajit Chakrabarti
Two-dimensional (2D) convolution is a fundamental operation widely employed in various fields such as image processing, computer vision, and medical imaging. Its capacity to extract significant features from spatial data is critical for applications including edge detection, object recognition, and the detection of tumors in medical scans. Furthermore, 2D convolution is integral to natural language processing, signal processing, robotics, and biometrics, which highlights its extensive applicability in contemporary technological advancements. This article examines three innovative methodologies—traditional multiplication and addition, systolic array-based multiplication, and Winograd-based multiplication—integrated within convolution methods to facilitate the design of deep neural network accelerators while optimizing performance through the approximation of multiplication and addition operations. The hardware implementation of 2D convolution presents notable benefits such as enhanced processing speed, reduced latency, and increased energy efficiency. By utilizing specialized hardware architectures, parallel processing capabilities are significantly improved, resulting in greater throughput and scalability. The functionality of all convolution layers follows the expected trend, and their validation has been done using a publicly available dataset. The proposed design reduces 11.2% of logic gate usage and other hardware elements including DSP and BRAM blocks, resulting in 66.93% overall resource consumption. These improvements are particularly vital for real-time applications such as video analysis and autonomous systems, where prompt decision-making is essential.