AND-Logic embedded 7T SRAM-based backplane circuit for low-power micro-displays

The micro-display market is expanding rapidly due to the increasing adoption of smartwatches and VR/AR head-mounted devices, creating strong demand for ultra-low-power display solutions to prolong battery life. Among various micro-display architectures, the digitally driven Pulse-Width Modulation (PWM) technique is preferred on CMOS backplanes due to its immunity to analog storage errors and the elimination of power-hungry digital-to-analog converters (DACs). However, conventional PWM-based digital driving schemes require repeated pixel programming within each frame, causing large column-line capacitance switching and substantial power dissipation in the display backplane. This paper presents an AND-Logic embedded 7T SRAM memory-based backplane circuit that minimizes pixel programming to only twice per frame, significantly reducing column line transitions and driver power. Fabricated in 65-nm CMOS, the proposed design achieves an 18.6% reduction in display backplane power compared to the conventional architecture. Furthermore, compared to the prior 8T AND-Logic embedded SRAM, the proposed SRAM cell achieves a 12.7% reduction in pixel memory area and a 4.9% reduction in backplane’s power consumption according to post-layout simulations, demonstrating its suitability for compact, power-efficient micro-display systems.