Phase-aware Inverse Design for Silicon Photonic Logic Gates

Inverse design has emerged as a powerful strategy for realizing compact photonic devices; however, its application to logic operations remains constrained by challenges in physical interpretability, architectural generality, and experimental validation. This work introduces an experimentally validated, unified, and physics-driven inverse design framework that implements all fundamental Boolean logic gates within a single silicon photonic architecture. Devices are fabricated within a 2 x 2 um^2 design region on a silicon-on-insulator platform, representing one of the smallest areas reported for photonic logic elements. By integrating amplitude, phase, and energy conservation into a composite figure of merit, the proposed approach enables direct control over constructive and destructive interference. Consequently, all logic functions, including XOR and three-input NAND/NOR operations, are achieved using a standardized configuration with two logical inputs and a bias port. Experimental results exhibit good agreement with numerical simulations across the C-band, confirming both the predictive accuracy and fabrication robustness of the method. Performance benchmarking reveals competitive contrast ratios compared to previous implementations, while providing a unified and scalable design strategy. These findings establish a physically interpretable and experimentally validated paradigm for inverse-designed photonic logic, advancing the development of compact, integrated optical computing systems.