CYCLIC CODE-BASED FINITE FIELD MULTIPLIER ARCHITECTURES FOR CLASSICAL AND POST-QUANTUM CRYPTOGRAPHY

Cryptographic hardware is exposed to both accidental and deliberately injected faults, making concurrent fault detection an essential safeguard. Most such hardware operates over finite fields GF(2^m), and within this arithmetic, multiplication is the most complex operation and the one most frequently targeted by attackers. This report presents fault-detection architectures for polynomialbasis finite-field multipliers built on systematic cyclic codes, applied to the fields used by classical and post-quantum cryptosystems — the Advanced Encryption Standard (AES), the Welch-Gong stream ciphers WG-16 and WG-29, and the McEliece codebased cryptosystem. The proposed schemes are embedded directly into the original multiplier datapaths and implemented on the AMD/Xilinx Artix-7 FPGA device xc7a12tcpg238-3, where their area, latency and error-coverage overheads are compared against unprotected baseline designs and prior fault-detection work, showing that nearcomplete error coverage is achievable at overhead levels suitable for resource-constrained embedded systems.