CHIP-LEVEL DESIGN OF A TURBO ENCODER FOR IN-VEHICLE COMMUNICATION SYSTEM

This report presents a chip-level design for a turbo encoder used for forward error correction (FEC) in an automotive in-vehicle system (IVS) module. The encoder is implemented on an FPGA, and both serial and parallel computation strategies for the encoding datapath are analyzed and compared. The proposed rate-1/3 turbo encoder combines two recursive systematic convolutional (RSC) encoders with a quadratic permutation polynomial (QPP) interleaver, built as a modular, parameterizable datapath suited to the power, area and real-time requirements of automotive electronics. Restructuring the design from a serial to a parallel computation approach is shown analytically to cut processing time substantially while also reducing logic resource usage, improving throughput and shrinking chip area. The design was developed, simulated and verified in Xilinx ISE using Verilog HDL, and is shown to be well suited for integration into a larger IVS chip on a single programmable device.