Hardware accelerator design and implement for convolutional neural network based on SOC_FPGA

In the era of big data, with the daily generation of massive data and the wide application of data mining algorithms, accelerating data storage and processing has become an important issue that both the academic community and the industrial sector need to address. The traditional CPU and GPU hardware acceleration methods are insufficient in some scenarios that require high real-time performance and low power consumption, especially in areas such as unmanned aircraft and intelligent cameras. However, the SOC_FPGA not only integrates the rich logic resources of FPGA but also carries an ARM processor, featuring flexible design, high speed, low power consumption, and portability, which is very conducive to the rapid deployment of applications in mobile terminals. This research addresses this issue by designing a high-performance and low-power computing acceleration module for convolutional neural networks using the SOC_FPGA platform and conducted image classification experiments based on the ImageNet dataset. The experimental results show that this design can ensure that the model's classification recognition accuracy reaches over 80%, while the processing rate of input image data can reach 218.76FPS (figures per second), and the maximum system power consumption is 4.8W. Compared with other platforms, it has advantages in both acceleration effect and system power consumption.