Design and Process of 3D MEMS Packaging

The design and assembly process of 10 different 3D MEMS packages will be presented and discussed in this study. These 3D MEMS packages integrate the MEMS devices from the MEMS wafer (with either wirebonding pads, or solder-bumped TSV (through silicon via) substrate, or solder-bumped flip chip without TSV), the ASIC chips from the ASIC wafer (with either TSV or without), and the cavity package cap from the cap wafer (with either TSV or without). The assembly process consists of release (etching), singulation, wire bonding, flip chip, TSV, cavity etching, chip-to-wafer (C2W) bonding and wafer-to-wafer (W2W) bonding. It can be shown that these packages lead to small packaging foot-print, high electrical performance, and potentially low cost.