Porous Silicon and Silicon Nanowires for On-Chip Supercapacitor Electrodes: A Review

Finding efficient ways to store energy is a current topic both at the macro level and at the microscale. As silicon plates are the main platform for the integration of microelectronic devices, it is reasonable to use the silicon structures as the active materials for on-chip microcapacitors. Porous silicon (pSi) and silicon nanowires (SiNWs) are ideal candidates for planar electrodes because these layers are directly embedded into the silicon wafer. The review contains a brief summary of the formation features of pSi/SiNW and their electrochemical performance. The structural characteristics of the silicon matrix (depth and morphology) that influence capacitive electrode properties are examined comprehensively for the first time. Particular attention is given to additional coatings on the pore/wire surface. Various ways of depositing metal, carbon, and polymer layers are considered in detail. Different approaches to filling the silicon matrix are explored. Focusing on pSi/SiNWs coatings allows us to identify the effect of the structure, crystallinity, and methods of additional layer deposition on capacitance, cycling stability, and charge transport of modified electrodes. Although fabrication processes for planar microcapacitors based on pSi/SiNWs are currently underdeveloped, the specific requirements and possible challenges of on-chip integration are discussed and proposed.