High-Efficiency Sub-100 nm Gate GaN HEMTs Enabled by Two-Step SiNx Layer Etching Technique.

This paper proposed a high-efficiency thin-barrier gallium nitride (GaN) high electron mobility transistor (HEMT) with scaled gate-length (Lg) for millimeter-wave (mmW) frequency applications. A two-step etching process is adopted in this work, where an Ar-free etching was used for the secondary etching (SE) step. After partial etching of the Silicon nitride (SiN) passivation layer in the gate foot region, the Lg can be stably controlled at <100 nm, the root mean square (RMS) roughness of the AlGaN barrier layer is 0.248 nm, and the mobility degradation has been effectively suppressed. The fabricated device achieved a maximum drain current density (IDS.max) of 1644.2 mA/mm, a peak transconductance (gm.max) of 764.1 mS/mm, and a current collapse ratio of 4.7%. In addition, the current gain cutoff frequency (fT) of 105.4 GHz and maximum oscillation frequency (fMAX) of 154.4 GHz were obtained at drain source voltage (Vds) of 8 V. Furthermore, at 30 GHz, the fabricated device achieved a saturated output power density (Psat) of 4.4 W/mm and a maximum power-added efficiency (PAEmax) of 66.0%, with a significant improvement of 15.7% and 5.3% compared with the device fabricated by Ar-containing etching, demonstrating the superiority of the Ar-free etching approach.