Energy-Efficient & Privacy-Preserving Adaptive Post-Quantum Secure Boot for Low-Power RISC-V IoT: A Hardware-Agnostic Approach with Empirical Validation

The advent of cryptographically relevant quantum computers threatens the classical public-key primitives (RSA, ECC) that currently secure the boot and over-the-air (OTA) update chains of billions of low-power Internet of Things (IoT) devices. NIST has also standardized the lattice-based post-quantum cryptography (PQC) algorithms, including "ML-KEM and ML-DSA" / "ML-KEM, ML-DSA, and SLH-DSA", but PQC secure-boot solutions for embedded systems either rely on dedicated hardware roots-of-trust that add to per-unit costs, or are based on static, non-adaptive benchmarks, which are unable to establish a tangible security/benefit-cost ratio for software-only implementations. This paper proposes AdaptivePQC-Boot as a hardware-agnostic, hybrid classical-PQC secure-boot and OTA-update scheme for commodity RISC-V microcontrollers that (i) requires no dedicated security silicon, relying on RISC-V Physical Memory Protection (PMP) for software-based attestation, (ii) adaptively switches between classical, hybrid, and full-PQC cryptographic modes based on battery level and threat severity, retaining energy budget and device privacy guarantees, and (iii) empirically quantifies the resulting trade-offs. The verification scheme is implemented and evaluated on an ESP32-C6 RISC-V IoT board: Mean time and estimated energy cost of verification are monotonically increasing from Classical (6.46 ms, 0.155 mJ) to Hybrid (9.49 ms, 0.464 mJ) and then to Full-PQC (13.23 ms, 0.774 mJ) across n=12 repeated verification cycles. The adaptive switch-engine saves 56.7% energy compared to an always-Full-PQC baseline in a 12-cycle battery-drain simulation with 4.02 mJ versus 9.29 mJ respectively. The results place the proposed scheme as a viable, clear and energy efficient replacement to hardware-based PQC for cost-limited consumer, industrial-retrofit and privacy-sensitive IoT applications.