Design of High Performance Second-Generation Voltage Conveyor Using Adaptive Bias Technique and its Application

This paper presents a high-performance class AB second-generation voltage conveyor (VCII), optimized for modern integrated circuit applications. The proposed VCII architecture comprises of a current buffer at the input stage, followed by a voltage buffer. The proposed VCII incorporates slew rate and bandwidth enhancement techniques to optimize its overall performance. Specifically, adaptive biasing, resistive compensation, and a super-transistor configuration are employed to enhance the performance of the conveyor. The super-transistor configuration provides a low output impedance whereas adaptive biasing and resistive compensation technique provides slew rate enhancement and bandwidth extension along with high dynamic range in proposed VCII. Proposed VCII circuits simulated in Cadence Virtuoso environment using TSMC 0.18-μm GPDK technology file and operate at a low supply voltage of ±0.8 V, achieving bandwidths of 319 MHz and 389 MHz for the voltage and current transfer functions, respectively. The proposed VCII consumes 39 µW of static power and exhibits an average slew rate of 2.11 V/µs, demonstrating high-speed and low-power performance. The impedances at Y, Z and X terminals were computed as 63.68 Ω, 23 Ω, and 325 KΩ, respectively. The layout of the proposed VCII has been designed, occupying an area of 2266.041 µm². Furthermore, the performance of proposed VCII is validated through its application in a half-wave rectifier circuit, demonstrating its suitability for analog signal processing applications. Monte Carlo analysis considering device mismatch and PVT variations has been performed to demonstrate the robustness of the proposed circuit.