Fault modeling and test generation methods for complex digital circuits

It is shown that the process of determining the serviceability of any logic block or microcircuit as a whole consists in monitoring its parameters at the output or some other points available for measurement and comparing them with the required ones when applying test actions to the inputs. At the same time, the main components of this process are the generation of test sequences and the implementation of test diagnostics, which is based on the modeling of malfunctions that were investigated in this work. The aim of the work is to develop a high-performance interactive subsystem for diagnostics and its integration into CAD. The main objectives of the research are: fault modeling and algorithmization of tasks of ran-dom and directed generation of test sequences; implementa-tion of tasks of generation and verification; investigation of the effectiveness of software tools and the methodology of their use. An algorithm for accelerated fault modeling and a block diagram of an accelerated simulation algorithm have been developed. The diagram illustrates an example of a re-converging path. The model of a faulty logic circuit is considered. The method of random test generation is used for research. A structural block diagram of an algorithm for random generation of a test sequence has been devel-oped. An increase in the efficiency of algorithms for di-rected test generation is considered. A brief scheme of the SF algorithm is constructed. The architecture of the diag-nostic subsystem as part of an integrated VLSI CAD sys-tem, including a number of target subsystems, a specialized logic modeling accelerator connected by a local network, has been developed and proposed.