Characterizing conditional quantum dynamics on superconducting quantum processors

Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of $$\mathcal {F}_p^{\text {CX}} = 93.02\%$$ F p CX = 93.02 % and correctly prepared the target state with $$P_{00}^{\text {CX}} = 92.40\%$$ P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved $$\mathcal {F}_p^{\text {CZ}} = 92.59\%$$ F p CZ = 92.59 % with superior state-preparation fidelity of $$P_{00}^{\text {CZ}} = 97.08\%$$ P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.