PoSyn: Secure Power Side-Channel Aware Synthesis

Power side-channel (PSC) attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Traditional countermeasures, such as masking, face challenges like complex synthesis integration, high area overhead, and vulnerability to optimization removal during logic synthesis. To address these issues, we introduce proposed side-channel aware synthesis (PoSyn), a novel logic synthesis framework designed to enhance cryptographic hardware’s resistance against PSC attacks. Our approach focuses on the optimal bipartite mapping of vulnerable register transfer level (RTL) components to standard cells from the technology library to minimize PSC leakage. By employing a cost function that integrates key characteristics from the RTL design and the standard cell library, we strategically modify the mapping criteria during the conversion of RTL designs into standard cell netlists without altering the design functionality. Furthermore, PoSyn is theoretically shown to minimize mutual information leakage, further reinforcing its security against PSC vulnerabilities. PoSyn is evaluated on a variety of cryptographic hardware, including AES, RSA, PRESENT, and postquantum cryptography algorithms like Saber and CRYSTALS-Kyber across 65-, 45-, and 15-nm nodes. Our experimental results demonstrate a significant reduction of success rates for differential power analysis (DPA) and correlation power analysis (CPA) attacks, as low as 3% and 6%, respectively. Furthermore, test vector leakage assessment (TVLA) confirms that the synthesized netlists exhibit negligible leakage. Moreover, compared to traditional countermeasures such as masking and shuffling, PoSyn achieves notably lowers the success rates, achieving a reduction by up to 72%, while simultaneously enhancing area efficiency by as much as$3.79\times $. These results highlight the effectiveness of PoSyn in securing cryptographic hardware with minimal impact on area and performance.