A 12-bit 40-MS/s Pipelined SAR ADC for Ultrasonic Nondestructive Testing Applications

This paper presents a 12-bit, 40-MS/s hybrid pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) for ultrasonic nondestructive testing (NDT) applications. The first stage utilizes an asynchronous SAR ADC with 8-bit resolution, while the second stage employs a time-domain ADC incorporating a ring-assisted time-to-digital converter (TDC), resulting in a highly digital and power-efficient implementation. A feedforward floating inverter amplifier (FIA) amplifies the first-stage residual voltage, enhancing the input signal amplitude for the second stage while suppressing TDC quantization noise interference, thereby simplifying the second-stage design. Fabricated in 65-nm CMOS technology, the ADC occupies 0.6 mm² and consumes 1.58 mW from a 1.2-V supply. With a 4.88-MHz input signal, the prototype achieves 65.1-dB peak signal-to-noise-and-distortion ratio (SNDR) and 79.2-dB spurious-free dynamic range (SFDR), yielding a Walden-based figure of merit (FoM) of 29.2 fJ/conversion-step.