Improving Reliability of 40-nm RRAM Chip Through Radical-Enhanced Annealing for Sidewall and Interface Engineering

Reliability stands as a pivotal bottleneck for the commercialization of emerging nonvolatile memories, including resistive random access memory (RRAM). In this work, we successfully demonstrated a 40-nm HfOx-based RRAM chip featuring superior wafer-level uniformity and robust array-level reliability enabled by sidewall and interface engineering. Aradical-enhanced annealing (REA) process was introduced to tackle the dry etching-induced reliability issues and enhance the control over the switching behavior of conductive filaments (CFs). With REA, we achieved$10.86\times $largeron/offratio compared with the baseline without REA, along with 100k cycle endurance, ten-year retention at$85~^{\circ }$C, and over$10^{{9}}$cycles read disturbance immunity. The characteristics of the RRAM chip’s reliability and the mechanism for the impact of REA on the device performance were clarified in detail through extensive material characterization, structural simulation, and electrical testing. This work provides an effective scheme to address the reliability issue of RRAM and also promotes the large-scale integration of RRAM toward more advanced technology nodes.