Leakage Current Reduction Strategy for Low-Power Low-Voltage Intrinsically Stretchable Organic Transistor

Low-voltage operation and minimal power consumption in intrinsically stretchable organic field-effect transistors (OFETs), ensure user safety and device portability, and hence are imperative for on-body/wearable applications. However, low-voltage OFETs commonly suffer from high leakage current, leading to high power consumption. In this work, we propose a general strategy for low-power, low-voltage intrinsically stretchable OFETs, by combining an additive 34.7-nm SEBS layer on high-$k$PUU dielectric with the patterned semiconductor, to reduce the vertical tunneling leakage current and lateral parasitic leakage current, respectively. The resulting OFET exhibits a remarkable reduction in leakage current by approximately three orders of magnitude, and the waste power consumption as low as${9}.{38}\times {10} ^{-{9}}$W, with high mobility of 2.83 cm2V${}^{\text {- {1}}}$s${}^{-{1}}$and low operating voltage at –10 V. Stretched to 100%, the OFETs still operated at a stable operating voltage of –10 V, with only ~15% variation in waste power consumption. Our work provides a generalizable strategy for designing low-power-consumption low-voltage skin-like electronic devices.