Design and Analysis of a Compact CMOS SOI Power Amplifier With 29.2-dBm <i>P</i> _SAT and 44.4% PAE for FR3 5G-Advanced/6G Beamforming Systems

This article presents a compact, high-efficiency power amplifier (PA) for frequency range 3 (FR3) beamformer integrated circuits (BFICs) targeting 5G-Advanced and 6G systems. To address the output power, efficiency, and integration challenges of silicon-based PAs in high-density antenna arrays, an extended cascode core (ECC) leveraging floating-body (FB) silicon-on-insulator (SOI) transistors is adopted to provide improved power handling with a stable breakdown margin, andRC-feedback networks that further enhance broadband stability and output matching. A triple-coupled 4-to-1 folded transformer (FT) with odd-/even-mode co-optimization enables efficient power combining, incorporating an embedded$\pi $-network that suppresses the 2nd harmonic ($2{f_{0}}$) to sustain high output power and efficiency in a compact footprint. Fabricated in the 0.13-$\mu $m CMOS SOI technology, the PA achieves a 3-dB bandwidth of$9.0{-}13.5$GHz, 29.2dBm saturated output power ($P_{\text {SAT}}$), and 44.4% peak power-added efficiency (PAE). The core area is 0.697mm2, corresponding to a 1193.3 mW/mm2power density (PD). It supports 64-QAM modulation at an average power of 22.6dBm with an error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) of −25dB and −31dBc, respectively. The PA exhibits amplitude-to-phase (AM–PM) distortion below 2.5°/2.1°/1.8° at 10/11/12GHz up to 1-dB compression point ($P_{\text {1 dB}}$), and${\lt } {-}36$dBc 2nd-/3rd-harmonic suppression across the band. The PA achieves state-of-the-art PAE and PD among FR3-band silicon-based PAs with competitive$P_{\text {SAT}}$, offering an integration-friendly, energy-efficient solution for massive multiple-input multiple-output (MIMO) transmitters in next-generation wireless systems.