First results of a monolithic active pixel sensor with internal signal gain fully integrated in a 180 nm CMOS technology

Abstract Dense tracking environments in experiments at CERN's High-Luminosity LHC and future FCC experiments call for an increased use of timing information in addition to the position measurement of pixel detectors. This adds one dimension to the information available, and is essential for pile-up mitigation at high luminosity. The CASSIA sensor project ( C MOS A ctive S en S or with I nternal A mplification) focuses on the development of pixel matrices with internal charge multiplication, based on monolithic CMOS sensor technologies, suitable for application as charged particle tracking and timing detectors. CMOS sensors with in-pixel internal amplification would provide higher signal amplitudes, an improved signal-to-noise ratio, better time resolution and increased sensitivity, making them attractive for high-radiation environments. Their monolithic integration in small pixels reduces the parallel capacitance presented to a front-end amplifier and the power dissipation making it suitable for fine-pitch low-power detectors. Fast signal rise time due to internal charge amplification improves the response time and timing resolution, all of which make such a technology attractive for future 4D tracking applications in HEP experiments. This paper presents the first results of the CASSIA sensor, a novel MAPS which uses gain layers fully integrated in a 180nm imaging process to achieve internal signal amplification. In the first measurements presented here we demonstrate the gain behaviour of different pixel implant designs and show that the sensor can be operated as LGAD sensor with low gain in proportional mode at lower voltages and as SPAD sensor at higher voltages.