An 8.5−14 GHz fractional-N dual-path SPD/PFD PLL with a complementary DTC pair in 7 nm FinFET

Abstract In fractional-N phase-locked loops, minimizing the integral nonlinearity (INL) of the digital-to-time converter (DTC) is crucial since it directly limits PLL performance. Considering the trade-off between DTC delay range and linearity, this paper presents a fractional-N dual-path SPD/PFD PLL (DP-SPFDPLL) with a complementary DTC pair. Controlled by the complementary control words, two DTCs are introduced before the two inputs of the phase detector for DTC range reduction and INL cancellation. The required DTC range is further halved by using differential VCO outputs to retime the frequency divider output. The overall design collectively achieves a 4× reduction in DTC range requirement. Fabricated in 7 nm FinFET, the DP-SPFDPLL achieves 118 fs RMS jitter and −247.5 dB figure-of-merit.