CMOS-compatible Si/Pd ohmic contact to n-InP for Si photonics

Abstract Abstract: Here, a CMOS-compatible ohmic contact scheme to n-type InP was reported. The selected materials are Si and Pd, which were deposited successively on n-InP epilayer (100 nm) on semi-insulating InP substrate to form a structure of Si (130 nm)/Pd (70 nm)/ n-InP (100 nm)/ semi-insulating InP substrate. Good ohmic contacts were obtained across a broad 400-500 ℃ temperature window by using rapid thermal annealing and the resulting specific contact resistivity is on the order of 10-5 Ω·cm², where the lowest value is 2.31×10-5 Ω·cm² when annealed at 500 ℃. Secondary ion mass spectrometry, energy-dispersive X-ray spectroscopy, X-ray diffraction, and Hall-effect measurements confirm that ohmic contact formation is attributed to a synergistic mechanism: (1) Si diffusion enabling heavy n-type doping in the InP epilayer, and (2) complete Pd-Si intermetallic layer formation.