Topology optimization design of solid-state transformer multilevel converters for high-efficiency data centers

Electricity demand and carbon pressure in modern data centres have exposed the limits of the line-frequency transformer in the medium-voltage distribution chain, and the solid-state transformer (SST) offers a credible route past them. This paper develops an SST multilevel converter topology shaped around the operating envelope of a high-efficiency data centre. We propose a hybrid cascaded H-bridge whose cells each embed a three-level flying-capacitor leg (CHB–FC), populate those legs with 1.7 kV SiC MOSFETs, and couple every cell to a series-resonant dual-active-bridge isolation stage; the arrangement halves per-device voltage stress and cuts the cell count relative to a conventional CHB–DAB baseline. Figure 1 presents the converter as a device-level circuit schematic, since the redundant switching states that balance the clamp capacitor are legible only at that level of detail. Around this topology we formulate a five-objective design problem—mission-profile-weighted efficiency, power density, cost, reliability and transient stability—subject to voltage, thermal and CISPR 11 EMI constraints. An improved NSGA-II with adaptive operator scheduling and archive-based elitism searches the resulting mixed-integer space, which spans eight power-stage variables together with the four controller gains appended by the stability objective, and under a matched evaluation budget recovers a Pareto front whose hypervolume exceeds that of standard NSGA-II by 9%. That figure comes from a single run and is reported as an observation, not as a statistically established advantage. MATLAB/Simulink–PLECS co-simulation predicts 98.7% efficiency at 50% loading and 1.42% THD on the medium-voltage side, ahead of CHB–DAB and MMC–DAB references. A 10 kV/750 V/100 kW scaled prototype returns 98.57% measured full-load efficiency, with a combined standard uncertainty near ± 0.05 percentage points, and keeps hotspot temperatures and EMI margins inside the design constraints. Simulated and measured quantities are kept apart throughout: 98.7% is a model prediction, 98.57% an instrument reading, and the 0.13-point gap between them is traced to busbar, auxiliary and winding effects. The solver code, the instrument records and the numerical data behind every figure accompany the paper as related files.