Xiaomeng Liu, Xiangsheng Wang, Yanpeng Song, Yiwen Zhang, Hailing Wang, Yifei Ma, Ying Zhang, Xin Hu, Wenhao Zhang, Han Wang, Jiajun Xu, Zhenzhen Kong, Bowen Dong, Guilei Wang, Chao Zhao
Overall, this work provides experimental insights into the degradation evolution, optimization potential, and remaining limitations of 300-period Si/SiGe SLs on 12-inch wafers, offering guidance for further scaling of Si/SiGe epitaxy toward future 3D DRAM applications.
To overcome the scaling limits of conventional dynamic random-access memory (DRAM), three-dimensional DRAM (3D DRAM) has been proposed for next-generation high-density memory. Multi-period Si/SiGe superlattices (SLs) are key candidates for vertically stacked channel structures, but their high-period stacking capability is limited by degradation of structural integrity and crystalline quality. In this work, 300-period Si/SiGe SLs with different Ge contents (∼ 25 and ∼ 15%) were grown on 12-inch Si wafers using reduced-pressure chemical vapor deposition (RPCVD), achieving total film thicknesses exceeding ∼ 14 μm. A Si/Si0.75Ge0.25 SL was first fabricated and systematically characterized, revealing partial strain relaxation, degradation of vertical periodicity, and within-wafer non-uniformity. Subsequently, a 300-period Si/Si0.85Ge0.15 SL with reduced effective Ge content was grown under optimized process conditions. Compared with the Si/Si0.75Ge0.25 structure, the Si/Si0.85Ge0.15 SL exhibits improved layer-to-layer thickness control, more stable composition profiles, and enhanced within-wafer uniformity. However, partial strain relaxation and threading dislocations are still observed. Overall, this work provides experimental insights into the degradation evolution, optimization potential, and remaining limitations of 300-period Si/SiGe SLs on 12-inch wafers, offering guidance for further scaling of Si/SiGe epitaxy toward future 3D DRAM applications.