Interface-Controlled High-Speed, Low-Power SET Process in Thermally Stable In ₃ Sb ₁ Te ₂ -Based Phase Change Memory Devices

The transition from the amorphous to crystalline phase (SET state) in phase-change random access memory (PCRAM) devices is a time-limiting process that governs overall switching speed. This study demonstrates that the switching speed and power consumption for the SET process are not solely determined by the intrinsic properties of the phase-change material (PCM) but are also critically influenced by the nature of the electrode-PCM interface. We observed that sourcing voltage from the higher Schottky metal-PCM interface and sinking it at the lower Schottky metal-PCM interface, defined as the good polarity, enables a high-speed, low-power SET process. Nevertheless, when the polarity is reversed, with voltage sourced from the lower Schottky contact and sunk at the higher Schottky interface (bad polarity), the device reverts to its initial high-resistance state under identical pulse conditions. In such cases, completing the SET process requires longer pulse durations and increased energy consumption. Temperature-dependent electrical measurements support these findings and underscore the critical influence of the metal-PCM interface on SET performance. These effects were examined with a pore-type device architecture employing a thermally stable, single-phase In 3 Sb 1 Te 2 (IST). IST demonstrates superior resistance contrast and higher thermal stability compared to conventional Ge 2 Sb 2 Te 5 (GST) alloys. Therefore, these results offer critical insights into selecting appropriate electrode materials and optimizing device polarity. They also establish a framework for modeling interface-controlled high-speed and low-power SET process of PCM-based devices.