Ultrastable 50 nm Top-Gate In2O3 Transistors with ΔVTH < 0.1 mV under 104 s Bias Stress Enabled by Annealing-Free Dielectric Engineering.

We demonstrate ultrastable 50 nm top-gate In2O3 thin-film transistors with an unprecedented near-zero threshold-voltage shift (ΔVTH < 0.1 mV) under 104 s bias stress. The devices are fabricated using an annealing-free, low-temperature process compatible with back-end-of-line (BEOL) integration, delivering high electrical performance, including a maximum drain current of 700 μA/μm and a minimum subthreshold swing of 64.4 mV/dec for a channel length (LCH) of 50 nm. This outstanding stability is enabled by in situ Ar-assisted plasma during plasma-enhanced atomic layer deposition (PE-ALD) of HfO2, which effectively suppresses defect states and passivates the In2O3/HfO2 interface, resulting in a low-defect gate stack. Furthermore, positive/negative bias stress (PBS/NBS) on short-channel devices at 25 °C consistently exhibits negligible ΔVTH, highlighting robust bias-stress stability. This result demonstrates a breakthrough in achieving high reliability within a fully BEOL-compatible thermal budget.