Probabilistic Computing via Gate-Tunable Random Telegraph Noise.

Although probabilistic computing offers a route to quantum-inspired optimization at room temperature, existing probabilistic bits (p-bits) often depend on non-CMOS devices or circuit-intensive randomness. Here, we report a CMOS-compatible p-bit that harnesses intrinsic random telegraph noise (RTN) in a fully depleted silicon-on-insulator field-effect transistor to produce stochastic binary outputs with direct gate-voltage control. The capture and emission dynamics follow Shockley-Read-Hall (SRH) kinetics, yielding a quantitative sigmoid bias-to-probability transfer, and the dwell-time statistics exhibit Poisson behavior consistent with memoryless switching. Pairwise statistical independence between independently measured RTN streams is supported through probabilistic Boolean operations and cross-correlation analysis. Using the experimentally derived RTN probability response, we perform an RTN-derived numerical emulation of simulated annealing for the two-dimensional hydrophobic-polar protein-folding benchmark, reaching low-energy configurations with fewer stochastic update iterations than the number of candidate conformations evaluated by exhaustive enumeration. We further map the same update pipeline into a digital logic design using integer energy evaluation and lookup-table probability mapping, providing a practical pathway toward CMOS-based probabilistic accelerators. Collectively, these results elevate intrinsic transistor noise from an unwanted artifact to a gate-tunable, CMOS-compatible stochastic primitive, providing a physically grounded pathway toward CMOS-based probabilistic processors.