Hyosik Jo, Yunseok Kim, Seulwon Choi, Ilhan Yoo, Minji Han, Jung‐El Ryu, Hwanyeol Park
The relentless scaling of semiconductor devices demands advanced patterning strategies for overcoming the intrinsic limitations of conventional top-down lithography. In this context, area-selective atomic layer deposition (AS-ALD) has emerged as a promising bottom-up technique for achieving nanoscale pattern fidelity by confining the growth of thin films to predefined surfaces while suppressing nucleation on non-growth regions. Leveraging the self-limiting surface chemistry of ALD, AS-ALD provides intrinsic self-alignment, reduces edge placement errors, and minimizes multi-patterning steps, thereby offering a scalable pathway for next-generation integrated circuits. This review provides a comprehensive summary of recent advances in AS-ALD, emphasizing three main approaches: (i) inhibitor-free strategies that exploit intrinsic or activation-induced reactivity differences; (ii) inhibitor-based techniques employing self-assembled monolayers, small-molecule inhibitors, and polymeric blocking layers; and (iii) emerging superlattice AS-ALD (SAS-ALD). Unlike conventional methods driven by chemical reactivity, SAS-ALD utilizes strain-driven kinetics on lateral 2D heterostructures to achieve atomic-level selectivity, representing a distinct paradigm in area-selective growth. The fundamental mechanisms governing the selectivity are discussed, along with representative material systems, integration challenges, and recovery schemes designed for sustaining long-cycle selectivity. SAS-ALD, which affords sub-10 nm pitch scalability, is highlighted as it holds significant promise for enabling future device architectures beyond Moore's Law. Finally, the critical remaining obstacles, such as defect-induced nucleation, inhibitor durability, and integration compatibility, as well as perspectives on how AS-ALD can evolve into a key enabler of advanced semiconductor manufacturing are presented.