Plasma Etching of Multilayer SiO ₂ /Si ₃ N ₄ Alternating Stacks Using Capacitively Coupled Plasma‐Reactive Ion Etching

Multilayer SiO 2 /Si 3 N 4 alternating stacks play a critical role in advanced semiconductor devices, including 3D NAND flash memory and next‐generation transistors such as the ultimate vertical gate‐all‐around (UVGAA) metal‐oxide‐semiconductor field‐effect transistor (MOSFET). While plasma dry etching of large‐scale patterns in 3D memory applications has been widely studied, the etching of small‐scale patterns (with feature sizes ranging from 200 to 1000 nm) in UVGAA MOSFET remains unexplored. In this work, we systematically investigated the plasma etching of small‐scale patterns in multilayer alternating SiO 2 /Si 3 N 4 stacks using capacitively coupled plasma reactive ion etching. The influence of key process parameters: gas composition, chamber pressure, gas flow rate, and radio frequency (RF) power on etch rate was examined. Intermittent etching was identified as an effective method to enhance the etch rate by mitigating heat accumulation. Furthermore, the pattern geometry can modulate the etching efficiency, and the results revealing that square patterns exhibit higher etch rates than rectangle patterns of equivalent area. The mask thickness influences the maximum etching depth in small‐scale patterns. This work advances plasma etching strategies for the fabrication of future 3D integrated circuits.